The present invention relates to a pseudo-noise sequence (to be referred to as a PN sequence hereinafter) generator.
A PN sequence means a code having a binary cyclic sequence in which the auto-correlation function takes only two values, and is disclosed in detail in SOLOMON W. GOLOMB, et al., "Digital Communications", PRENTICE-HALL, INC, pp. 17-32.
In order to obtain a PN sequence from parallel digital input signals, the following two conventional methods shown in FIGS. 1 and 2 are employed. In FIG. 1, parallel input signals A.sub.1 to A.sub.n are converted to a serial signal by a parallel-to-serial (P/S) converter 1, and is coded to a PN sequence by a conventional PN sequence generator 2. The obtained PN sequence is converted to parallel signals B.sub.1 to B.sub.n by a serial-to-parallel (S/P) converter 3. In FIG. 2, parallel input signals A.sub.1 to A.sub.n are respectively coded to a PN sequence by PN sequence generators 2, thus obtaining parallel PN sequence outputs B.sub.1 to B.sub.n. FIG. 3 shows the arrangement of the PN sequence generator 2 shown in FIGS. 1 and 2. In FIG. 3, an nth bit corresponding to the final stage of a shift register 22 having N stages (N: an arbitrary natural number) and an arbitrary bit are input to an exclusive-OR gate (to be referred to as an EXOR hereinafter) 23. The output from the EXOR 23 and an input signal a are input to an EXOR 21. The output from the EXOR 21 is output as a PN sequence b, and is also input to the first stage of the shift register 22.
In the conventional circuit shown in FIG. 1, if the number of parallel digital input signals is increased, only one PN sequence generator 2 is required, resulting in hardware and cost advantages. However, along with an increase/decrease in number of parallel digital input signals, the arrangements of the P/S converter 1 and the S/P converter 3 must be changed, and clock signals necessary for these converters must be prepared.
In contrast to this, in the conventional circuit shown in FIG. 2, no P/S and S/P converters nor timing signals therefor are required. However, the PN sequence generators 2 corresponding in number to parallel digital input signals must be prepared, resulting in hardware and cost disadvantages.
In both the circuits, since the shift register 22 is used, a processing time corresponding to a code length n is necessary, and an operating speed is low accordingly.
In the conventional circuit shown in FIG. 1, when all the stages D.sub.i (i=1 to n) of the shift register 22 are 0, if all the inputs A.sub.i (i=1 to n) are also 0, the outputs B.sub.i (i=1 to n) continuously generate an identical pattern of 0. If all the stages D.sub.i are 1 and all the inputs A.sub.i are 1, the outputs B.sub.i also continuously generate 1. This does not satisfy a condition that identical patterns corresponding to a period of the code length n necessary for a pseudo-noise signal of, e.g., a scrambler must not be generated. When the PN sequence is encrypted and added, the code length n of the PN sequence can be undesirably easily detected due to generation of identical patterns.
When the number n of signal lines to be subjected to parallel processing is to be arbitrarily changed, or when the code length n necessary when the PN sequence is used as a code is to be arbitrarily changed, the above conventional circuits cannot quickly cope with this.